Understanding cmp instruction

cmp arg2, arg1 performs the same operation as sub arg2, arg1 except that none of the operands are modified. The difference is not stored anywhere. However, the flags register is updated and can be used in a conditional jump, like jump-if-equal (JE), most often as the next instruction after the cmp. The advantage over other … Read more

x86 Assembly pointers

As has already been stated, wrapping brackets around an operand means that that operand is to be dereferenced, as if it were a pointer in C. In other words, the brackets mean that you are reading a value from (or storing a value into) that memory location, rather than reading that value directly. So, this: … Read more

Differences Between ARM Assembly and x86 Assembly [closed]

Main differences: ARM is a RISC style architecture – instructions have a regular size (32-bit for standard ARM and 16-bits for Thumb mode, though Thumb has some instructions that chew up 2 instruction ‘slots’) up through at least ARM v5 architecture (I’m not sure what v6 does), the interrupt model on ARM is vastly different … Read more

Physical or virtual addressing is used in processors x86/x86_64 for caching in the L1, L2 and L3?

The answer to your question is – it depends. That’s strictly a CPU design decision, which balances over the tradeoff between performance and complexity. Take for example recent Intel Core processors – they’re physically tagged and virtually indexed (at least according to http://www.realworldtech.com/sandy-bridge/7/). This means that the caches can only complete lookups in pure physical … Read more

about assembly CF(Carry) and OF(Overflow) flag

The distinction is in what instructions are used to manipulate the data, not the data itself. Modern computers (since circa 1970) use a representation of integer data called two’s-complement in which addition and subtraction work exactly the same on both signed and unsigned numbers. The difference in representation is the interpretation given to the most … Read more

Lost Cycles on Intel? An inconsistency between rdtsc and CPU_CLK_UNHALTED.REF_TSC

TL;DR The discrepancy you are observing between RDTSC and REFTSC and is due to TurboBoost P-state transitions. During these transitions, most of the core, including the fixed-function performance counter REF_TSC, is halted for approximately 20000-21000 cycles (8.5us), but rdtsc continues at its invariant frequency. rdtsc is probably in an isolated power and clock domain because … Read more

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