(Some of this is x86 and Intel-specific. Most of the key points apply to any CPU that does hardware page walks. I also discuss ISAs like MIPS that handle TLB misses with software.) Modern x86 microarchitectures have dedicated page-walk hardware. They can even speculatively do page-walks to load TLB entries before a TLB miss actually … Read more
The answer to your question is – it depends. That’s strictly a CPU design decision, which balances over the tradeoff between performance and complexity. Take for example recent Intel Core processors – they’re physically tagged and virtually indexed (at least according to http://www.realworldtech.com/sandy-bridge/7/). This means that the caches can only complete lookups in pure physical … Read more
This answer is by no means exhaustive but it may explain it enough to make things click. In virtual memory systems, there is a disconnect between logical and physical addresses. An application can be given a virtual address space of (let’s say) 4G. This is its usable memory and it’s free to use it as … Read more
Let me explain all these things step by step. The CPU generates the logical address, which contains the page number and the page offset. The page number is used to index into the page table, to get the corresponding page frame number, and once we have the page frame of the physical memory(also called main … Read more
A TLB (Translation Lookaside Buffer) is a cache of the translations from virtual memory addresses to physical memory addresses. When a processor changes the virtual-to-physical mapping of an address, it needs to tell the other processors to invalidate that mapping in their caches. That process is called a “TLB shootdown”.