TL;DR The discrepancy you are observing between RDTSC and REFTSC and is due to TurboBoost P-state transitions. During these transitions, most of the core, including the fixed-function performance counter REF_TSC, is halted for approximately 20000-21000 cycles (8.5us), but rdtsc continues at its invariant frequency. rdtsc is probably in an isolated power and clock domain because … Read more
X86_FEATURE_CONSTANT_TSC + X86_FEATURE_NONSTOP_TSC bits in cpuid (edx=x80000007, bit #8; check unsynchronized_tsc function of linux kernel for more checks) Intel’s Designer’s vol3b, section 16.11.1 Invariant TSC it says the following “16.11.1 Invariant TSC The time stamp counter in newer processors may support an enhancement, referred to as invariant TSC. Processor’s support for invariant TSC is indicated … Read more
Starting from GCC 4.5 and later, the __rdtsc() intrinsic is now supported by both MSVC and GCC. But the include that’s needed is different: #ifdef _WIN32 #include <intrin.h> #else #include <x86intrin.h> #endif Here’s the original answer before GCC 4.5. Pulled directly out of one of my projects: #include <stdint.h> // Windows #ifdef _WIN32 #include <intrin.h> … Read more
As mentioned in a comment, there’s a difference between a compiler barrier and a processor barrier. volatile and memory in the asm statement act as a compiler barrier, but the processor is still free to reorder instructions. Processor barrier are special instructions that must be explicitly given, e.g. rdtscp, cpuid, memory fence instructions (mfence, lfence, … Read more