3.1.1.1 Opcode Column in the Instruction Summary Table (Instructions without VEX Prefix) The “Opcode” column in the table above shows the object code produced for each form of the instruction. When possible, codes are given as hexadecimal bytes in the same order in which they appear in memory. Definitions of entries other than hexadecimal bytes … Read more
leal, or lea full name is “Load effective address” and it does exactly this: It does an address calculation. In your example the address calculation is very simple, because it just adds a offset to ebx and stores the result in eax: eax = ebx + 0x10 lea can do a lot more. It can … Read more
The physical address is calculated from 2 parts. i) segment address. ii) offset address. The CS(code segment register) is used to address the code segment of the memory i.e a location in the memory where the code is stored. The IP(Instruction pointer) contains the offset within the code segment of the memory. Hence CS:IP is … Read more
Assuming 32-bit x86, use the following function: get_eip: mov eax, [esp] ret Then, to get the value of EIP in EAX, simply: call get_eip
Updated I’ve got no explanation for you, since I’m on Haswell, but I do have code to share that might help you or someone else with Broadwell or Skylake hardware isolate your problem. If you could please run it on your machine and share the results, we could gain an insight into what’s happening to … Read more
MM registers are the registers used by the MMX instruction set, one of the first attempts to add (integer-only) SIMD to x86. They are 64 bit wide and they are actually aliases for the mantissa parts of the x87 registers (but they are not affected by the FPU top of the stack position); this was … Read more
Programming from the Ground Up (free book, highly recommended) x86 Assembly (wikibooks.org) Essential Resources for x86 Programmers
Phoronix tested the performance downside of -O2 -fno-omit-frame-pointer with x86-64 GCC 12.1 on a Zen 3 laptop CPU for multiple open-source programs, as proposed for Fedora 37. Most of them had performance regressions, a few of them very serious, although the biggest ones are probably some kind of fluke or other interaction. Geometric mean slowdown of 14% … Read more
It sounds like the atomic operations on memory will be executed directly on memory (RAM). Nope, as long as every possible observer in the system sees the operation as atomic, the operation can involve cache only. Satisfying this requirement is much more difficult for atomic read-modify-write operations (like lock add [mem], eax, especially with an … Read more
The square brackets essentially work like a dereference operator (e.g., like * in C). So, something like mov REG, x moves the value of x into REG, whereas mov REG, [x] moves the value of the memory location where x points to into REG. Note that if x is a label, its value is the … Read more