In practice, at the CPU level, there are instructions which can atomically update an int, and a good compiler will use these for std::atomic<int>. In contrast, there are are no instructions which can atomically update a vector of ints (for any architecture I am aware of), so there has got to be a mutex of … Read more
addr aIandF(addr r1) { addr tmp; int c; do { do { // r1 holds the address of the address // of the refcount tmp = *r1; // grab the address of the refcount if (!tmp) break; // if it’s null, bail // read current refcount // and acquire reservation c = lwarx(tmp); // now … Read more
I know your pain as I am one of the Architects of Dedoose. I have messed around with a lot of caching libraries and ended up building this one after much tribulation. The one assumption for this Cache Manager is that all collections stored by this class implement an interface to get a Guid as … Read more
Is the compiler free to cache the value of the atomic variable and unroll the loop? The compiler cannot cache the value of an atomic variable. However, since you are using std::memory_order_relaxed, that means the compiler is free to reorder loads and stores from/to this atomic variable with regards to other loads and stores. Also … Read more
As of C11 there is an optional Atomic library which provides atomic operations. This is portable to whatever platform that has a C11 compiler (like gcc-4.9) with this optional feature. The presence of the atomic can be checked with __STDC_NO_ATOMICS__and the presence of <stdatomic.h> atomic.c #include <stdio.h> #include <stdlib.h> #ifndef __STDC_NO_ATOMICS__ #include <stdatomic.h> #endif int … Read more
Doing a = 28 (with a being an int) is an atomic operation. But doing a++ is not an atomic operation because it requires a read of the value of a, an incrementation, and a write to a of the result. As a result, if you used a++ to implement a thread-safe counter, you could … Read more
You are wrong. There is no guarantee that ++ is atomic and neither is there for the compound assignment operators, or indeed for any C++ operation.
This recommendation is architecture-specific. It is true for x86 & x86_64 (in a low-level programming). You should also check that compiler don’t reorder your code. You can use “compiler memory barrier” for that. Low-level atomic read and writes for x86 is described in Intel Reference manuals “The Intel® 64 and IA-32 Architectures Software Developer’s Manual” … Read more
Although various answers cover bits and pieces of what the potential problem is and/or provide useful information, no answer correctly describes the potential issues for all three cases. In order to synchronize memory operations between threads, release and acquire barriers are used to specify ordering. In the diagram, memory operations A in thread 1 cannot … Read more