Although various answers cover bits and pieces of what the potential problem is and/or provide useful information, no answer correctly describes the potential issues for all three cases. In order to synchronize memory operations between threads, release and acquire barriers are used to specify ordering. In the diagram, memory operations A in thread 1 cannot … Read more
To answer all 5 questions: 1) A compiler fence (by itself, without a CPU fence) is only useful in two situations: To enforce memory order constraints between a single thread and asynchronous interrupt handler bound to that same thread (such as a signal handler). To enforce memory order constraints between multiple threads when it is … Read more
Summary CPU cores have special memory ordering buffers to assist them with out-of-order execution. These can be (and typically are) separate for loading and storing: LOBs for load-order buffers and SOBs for store-order buffers. The fencing operations chosen for the Unsafe API are were selected based on the following assumption: underlying processors will have separate … Read more
The simplest answer: you must use one of 3 fences (LFENCE, SFENCE, MFENCE) to provide one of 6 data Consistency: Relaxed Consume Acquire Release Acquire-Release Sequential C++11: Initially, you should consider this problem from the point of view of the degree of order of memory access, which is well documented and standardized in C++11. You … Read more
For performance gains modern CPUs often execute instructions out of order to make maximum use of the available silicon (including memory read/writes). Because the hardware enforces instructions integrity you never notice this in a single thread of execution. However for multiple threads or environments with volatile memory (memory mapped I/O for example) this can lead … Read more