The memory barriers present on the x86 architecture – but this is true in general – not only guarantee that all the previous1 loads, or stores, are completed before any subsequent load or store is executed – they also guarantee that the stores have became globally visible. By globally visible it is meant that other … Read more
“H” for “Hexadecimal”, base 16. 0009H = 9 decimal, 000AH = 10 decimal, 000FH = 15 decimal, 0010H = 16, 0020H = 32 et cetera.
It also depends on instruction mix. Your processor will have several computation units standing by at any time, and you’ll get maximum throughput if all of them are filled all the time. So, executing a loop of mul’s is just as fast as executing a loop or adds – but the same doesn’t hold if … Read more
Addition and subtraction are the same, as is the low-half of a multiply. A full multiply, however, is not. Simple example: In 32-bit twos-complement, -1 has the same representation as the unsigned quantity 2**32 – 1. However: -1 * -1 = +1 (2**32 – 1) * (2**32 – 1) = (2**64 – 2**33 + 1) … Read more
Rotates are required for bit shifts across multiple words. When you SHL the lower word, the high-order bit spills out into the carry. To complete the operation, you need to shift the higher word(s) while bringing in the carry to the low-order bit. RCL is the instruction that accomplishes this. High word Low word CF … Read more
You can’t access it directly because there’s no legitimate use case. Having any arbitrary instruction change eip would make branch prediction very difficult, and would probably open up a whole host of security issues. You can edit eip using jmp, call or ret. You just can’t directly read from or write to eip using normal … Read more
All-zero: pxor xmm0,xmm0 (or xorps xmm0,xmm0, one instruction-byte shorter.) There isn’t much difference on modern CPUs, but on Nehalem (before xor-zero elimination), the xorps uop could only run on port 5. I think that’s why compilers favour pxor-zeroing even for registers that will be used with FP instructions. All-ones: pcmpeqw xmm0,xmm0. This is the usual … Read more
Looks like the dissembler used short-hand for SAR EAX,1 which has an opcode of 0xD1F8. when the immediate is not 1, aka SAR EAX,xx, the opcode is 0xC1F8 xx, see the Intel Instruction reference, Vol. 2B, 4-353.
I’m going from memory here, so I may be off slightly on a detail or two. However, it should I hope be enough to get you going in the right direction. You’re going to need to tell the GCC assembler that your routine printSomething() is not defined in your assembly file. In ‘C’ you would … Read more
The best reference is the Intel Optimization Manual, which provides fairly detailed information on architectural hazards and instruction latencies for all recent Intel cores, as well as a good number of optimization examples. Another excellent reference is Agner Fog’s optimization resources, which have the virtue of also covering AMD cores. Note that specific cost models … Read more