A best practices approach suggested by peter-cordes is to see what gcc is going to make of your ‘what capabilities your cpu has’ by issuing the following: gcc -O3 -fverbose-asm -march=native -xc /dev/null -S -o- | less This command will provide information (all) about your cpu capabilities from the view of gcc, whom is going … Read more
All-zero: pxor xmm0,xmm0 (or xorps xmm0,xmm0, one instruction-byte shorter.) There isn’t much difference on modern CPUs, but on Nehalem (before xor-zero elimination), the xorps uop could only run on port 5. I think that’s why compilers favour pxor-zeroing even for registers that will be used with FP instructions. All-ones: pcmpeqw xmm0,xmm0. This is the usual … Read more
I would use a 4*double multiplication, then a hadd (which unfortunately adds only 2*2 floats in the upper and lower half), extract the upper half (a shuffle should work equally, maybe faster) and add it to the lower half. The result is in the low 64 bit of dotproduct. __m256d xy = _mm256_mul_pd( x, y … Read more
I have been studying measuring memory bandwidth for Intel processors with various operations and one of them is memcpy. I have done this on Core2, Ivy Bridge, and Haswell. I did most of my tests using C/C++ with intrinsics (see the code below – but I’m currently rewriting my tests in assembly). To write your … Read more
Per-element atomicity of vector load/store and gather/scatter?
They are complementary. Each new instruction set extension add new instructions and eventually a new programming model (new registers for example). None are deprecated, deprecating instructions is almost impossible to do for compatibility reasons. However some optional extensions may be absent or removed from newer models (like the FMA4 of AMD) if not very wide … Read more
For the visually inclined SIMD programmer, Stefano Tommesani’s site is the best introduction to x86 SIMD programming. http://www.tommesani.com/index.php/simd/46-sse-arithmetic.html The diagrams are only provided for MMX and SSE2, but once a learner gets proficient with SSE2, it is relatively easy to move on and read the formal specifications. Intel IA-32 Instructions beginning with A to M … Read more
This is because VSQRTPS (AVX instruction) takes exactly twice as many cycles as SQRTPS (SSE instruction) on a Sandy Bridge processor. See Agner Fog’s optimize guide: instruction tables, page 88. Instructions like square root and division don’t benefit from AVX. On the other hand, additions, multiplications, etc., do.
The compiler is allowed to fuse a separated add and multiply, even though this changes the final result (by making it more accurate). An FMA has only one rounding (it effectively keeps infinite precision for the internal temporary multiply result), while an ADD + MUL has two. The IEEE and C standards allow this when … Read more
Run this command: grep avx /proc/cpuinfo Or grep avx2 /proc/cpuinfo This will give you: flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush mmx fxsr sse sse2 ss syscall nx pdpe1gb rdtscp lm constant_tsc arch_perfmon rep_good nopl eagerfpu pni pclmulqdq vmx ssse3 cx16 pcid … Read more