duplicate symbols for architecture armv7
This can happen if you accidentally #import a .m file instead of the .h!
arm
Cross-compilation for Raspberry Pi in GCC. Where to start?
I found these instructions How to build a cross compiler for your Raspberry Pi. It is a great walk through using a crosstool-ng tool which simplifies configuring a cross-compiler build A LOT (it has a nice curses-based interface) and it supports GCC 4.7. Seems to work great!
Why does the ARM PC register point to the instruction after the next one to be executed?
It’s a nasty bit of legacy abstraction leakage. The original ARM design had a 3-stage pipeline (fetch-decode-execute). To simplify the design they chose to have the PC read as the value currently on the instruction fetch address lines, rather than that of the currently executing instruction from 2 cycles ago. Since most PC-relative addresses are … Read more
How does the linux kernel manage less than 1GB physical memory?
Not all virtual (linear) addresses must be mapped to anything. If the code accesses unmapped page, the page fault is risen. The physical page can be mapped to several virtual addresses simultaneously. In the 4 GB virtual memory there are 2 sections: 0x0… 0xbfffffff – is process virtual memory and 0xc0000000 .. 0xffffffff is a … Read more
cross compiler ldd
This is a bit of a kluge, but it’s the best solution I could find, and it really works quite well for basic use – just save this script as “arm-none-linux-gnueabi-ldd” with your other cross tools. #!/bin/sh arm-none-linux-gnueabi-readelf -a $1 | grep “Shared library:”
How to detect 386, amd64, arm, or arm64 OS architecture via shell/bash
uname -m prints values such as x86_64, i686, arm, or aarch64.
What is the ARM Thumb Instruction set?
The ARM processor has 2 instruction sets, the traditional ARM set, where the instructions are all 32-bit long, and the more condensed Thumb set, where most common instructions are 16-bit long (and some are 32-bit long). Which instruction set to run can be chosen by the developer, and only one set can be active (i.e. … Read more
Working of __asm__ __volatile__ (“” : : : “memory”)
asm volatile(“” ::: “memory”); creates a compiler level memory barrier forcing optimizer to not re-order memory accesses across the barrier. For example, if you need to access some address in a specific order (probably because that memory area is actually backed by a different device rather than a memory) you need to be able tell … Read more
arm gcc toolchain as arm-elf or arm-none-eabi, what is the difference?
Here is an excellent doc. Tool chains have a loose name convention like arch [-vendor] [-os] – eabi arch – refers to target architecture (which in our case is ARM) vendor – refers to toolchain supplier os – refers to the target operating system eabi – refers to Embedded Application Binary Interface some illustrations as … Read more
What registers to save in the ARM C calling convention?
It depends on the ABI for the platform you are compiling for. On Linux, there are two ARM ABIs; the old one and the new one. AFAIK, the new one (EABI) is in fact ARM’s AAPCS. The complete EABI definitions currently live here on ARM’s infocenter. From the AAPCS, ยง5.1.1: r0-r3 are the argument and … Read more