Summary The TLDR is that loads which miss all levels of the TLB (and so require a page walk) and which are separated by address unknown stores can’t execute in parallel, i.e., the loads are serialized and the memory level parallelism (MLP) factor is capped at 1. Effectively, the stores fence the loads, much as … Read more
It stands for “End Branch 64 bit” — or more precisely, Terminate Indirect Branch in 64 bit. Here is the operation: IF EndbranchEnabled(CPL) & EFER.LMA = 1 & CS.L = 1 IF CPL = 3 THEN IA32_U_CET.TRACKER = IDLE IA32_U_CET.SUPPRESS = 0 ELSE IA32_S_CET.TRACKER = IDLE IA32_S_CET.SUPPRESS = 0 FI FI; The instruction is otherwise … Read more
The System V AMD64 psABI document is maintained as LaTeX sources on GitLab. Similarly the i386 psABI is a separate GitLab repo. (Formerly on github). Those pages have info on where revisions are discussed. The x32 ABI (32-bit pointers in long mode) is part of the x86-64 aka AMD64 ABI doc. See Chapter 10: ILP32 … Read more
If you “fix” the alignment, all give the same assembly language output (with GCC): struct alignas(std::int64_t) Point { std::int32_t x, y; }; Demo As a note, some correct/legal ways to do some stuff (as type punning) is to use memcpy, so having specific optimization (or be more aggressive) when using that function seems logical.
The processor model as documented in the Intel/AMD processor manual is a pretty imperfect model for the real execution engine of a modern core. In particular, the notion of the processor registers does not match reality, there is no such thing as a EAX or RAX register. One primary job of the instruction decoder is … Read more
What you’re looking for is -M intel. Use it as follows. objdump -M intel -d program_name
rep; nop is indeed the same as the pause instruction (opcode F390). It might be used for assemblers which don’t support the pause instruction yet. On previous processors, this simply did nothing, just like nop but in two bytes. On new processors which support hyperthreading, it is used as a hint to the processor that … Read more
It’s a way to get code fix-ups (adjusting addresses based on where code sits in virtual memory, which may be different across different processes) without having to maintain a separate copy of the code for each process. The PLT, or procedure linkage table, is one of the structures which makes dynamic loading and linking easier … Read more
Alignment is a restriction on which memory positions a value’s first byte can be stored. (It is needed to improve performance on processors and to permit use of certain instructions that works only on data with particular alignment, for example SSE need to be aligned to 16 bytes, while AVX to 32 bytes.) Alignment of … Read more
This cannot be done with CMake. You have to generate two separate build folders. One for the x86 NMake build and one for the x64 NMake build. You cannot generate a single Visual Studio project covering both architectures with CMake, either. To build Visual Studio projects from the command line for both 32-bit and 64-bit … Read more