Long multi-byte NOPs: commonly understood macros or other notation
Recent GAS in binutils has a .nops N pseudo-instruction that expands to the requested number of bytes for the target: .nops size[, control]
x86-64
CMake -G Ninja on Windows specify x64
You have to set the compiler environment accordingly before calling Ninja generation. If you have Visual Studio 2013 installed at the standard installation path you call: “C:\Program Files (x86)\Microsoft Visual Studio 12.0\VC\vcvarsall.bat” x64 cmake.exe -G “Ninja” .. Edit: Thanks for the hint from @Antwane: “Or simply run CMake command from a Microsoft Visual Studio Command … Read more
32-bit absolute addresses no longer allowed in x86-64 Linux?
Your distro configured gcc with –enable-default-pie, so it’s making position-independent executables by default, (allowing for ASLR of the executable as well as libraries). Most distros are doing that, these days. You actually are making a shared object: PIE executables are sort of a hack using a shared object with an entry-point. The dynamic linker already … Read more
Porting 32 bit C++ code to 64 bit – is it worth it? Why?
x86-64 is a bit of a special case – for many architectures (eg. SPARC), compiling an application for 64 bit mode doesn’t give it any benefit unless it can profitably use more than 4GB of memory. All it does is increase the size of the binary, which can actually make the code slower if it … Read more
Are atomic variables lock-free?
The standard does not specify if atomic objects are lock-free. On a platform that doesn’t provide lock-free atomic operations for a type T, atomic<T> objects may be implemented using a mutex, which wouldn’t be lock-free. In that case, any containers using these objects in their implementation would not be lock-free either. The standard does provide … Read more
What is callq instruction?
It’s just call. Use Intel-syntax disassembly if you want to be able to look up instructions in the Intel/AMD manuals. (objdump -drwC -Mintel, GBD set disassembly-flavor intel, GCC -masm=intel) The q operand-size suffix does technically apply (it pushes a 64-bit return address and treats RIP as a 64-bit register), but there’s no way to override … Read more
Why are rbp and rsp called general purpose registers?
General purpose means all of these registers might be used with any instructions doing computation with general purpose registers while, for example, you cannot do whatever you want with the instruction pointer (RIP) or the flags register (RFLAGS). Some of these registers were envisioned to be used for specific use, and commonly are. The most … Read more
Why is %eax zeroed before a call to printf?
In the x86_64 ABI, if a function has variable arguments then AL (which is part of EAX) is expected to hold the number of vector registers used to hold arguments to that function. In your example: printf(“%d”, 1); has an integer argument so there’s no need for a vector register, hence AL is set to … Read more
How are the fs/gs registers used in Linux AMD64?
In x86-64 there are 3 TLS entries, two of them accesible via FS and GS, FS is used internally by glibc (in IA32 apparently FS is used by Wine and GS by glibc). Glibc makes its TLS entry point to a struct pthread that contains some internal structures for threading. Glibc usually refers to a … Read more
Why does this memory address %fs:0x28 ( fs[0x28] ) have a random value?
Both the FS and GS registers can be used as base-pointer addresses in order to access special operating system data-structures. So what you’re seeing is a value loaded at an offset from the value held in the FS register, and not bit manipulation of the contents of the FS register. Specifically what’s taking place, is … Read more