On x86 the NOP instruction is XCHG AX, AX The 2 mnemonic instructions assemble to the same binary op-code. (Actually, I suppose an assembler could use any xchg of a register with itself, but AX or EAX is what’s typically used for the nop as far as I know). xchg ax, ax has the properties … Read more
Bottom line: some technical limitations that amd64 has in using large addresses suggest dedicating the lower 2GiB of address space to code and data for efficiency. Thus the stack has been relocated out of this range. In i386 ABI1 stack is located before the code, growing from just under 0x8048000 downwards. Which provides “a little … Read more
MM registers are the registers used by the MMX instruction set, one of the first attempts to add (integer-only) SIMD to x86. They are 64 bit wide and they are actually aliases for the mantissa parts of the x87 registers (but they are not affected by the FPU top of the stack position); this was … Read more
Unless your 64-bit value can be encoded as a 32-bit-sign-extended immediate, you have to move it to a register first and then store. (Or do two separate 32-bit stores, or other worse workaround to get the bytes where you want them.) In NASM / Intel syntax, mov r64, 0x… picks a MOV encoding based on … Read more
The x86 instruction set (16, 32 or 64 bit, all variants/modes) guarantees / requires that instructions are at most 15 bytes. Anything beyond that will give an “invalid opcode”. You can’t achieve that without using redundant prefixes (e.g. multiple 0x66 or 0x67 prefixes, for example). The only instruction that actually takes 64-bits as a data … Read more
Fewest uops (front-end bandwidth): 1 uop, latency 3c (Intel) or 1c (Zen). Also smallest code-size, 5 bytes. popcnt %rax, %rax # 5 bytes, 1 uop for one port # if using a different dst, note the output dependency on Intel before ICL On most CPUs that have it at all, it’s 3c latency, 1c throughput … Read more
It depends on the exact CPU and operation. On 64-bit Pentium IVs, for example, multiplication of 64-bit registers was quite a bit slower. Core 2 and later CPUs have been designed for 64-bit operation from the ground up. Generally, even code written for a 64-bit platform uses 32-bit variables where values will fit in them. … Read more
use LDFLAGS= -L<Directory where the library resides> -l<library name> Like : LDFLAGS = -L. -lmine for ensuring static compilation you can also add LDFLAGS = -static Or you can just get rid of the whole library searching, and link with with it directly. Say you have main.c, fun.c and a static library libmine.a. Then you … Read more
TL;DR: You’re hobbled by bad defaults and compatibility with obsolete machines: Bad defaults are gcc setting errno for floating-point computations (despite this not being required by the C language), and compatibility with x86 machines that don’t have any better SSE instructions than SSE2. If you want decent code generation, add -fno-math-errno -msse4 to the compiler … Read more
In the context “retired” means: the instruction (microoperation, μop) leaves the “Retirement Unit”. It means that in Out-of-order CPU pipeline the instruction is finally executed and its results are correct and visible in the architectural state as if they execute in-order. In performance context this is the number you should check to compute how many … Read more