You are thinking in terms of sequential consistency, the strongest (and default) memory order. If this memory order is used, all accesses to atomic variables constitute a total order, and the assertion indeed cannot be triggered. However, in this program, a weaker memory order is used (release stores and acquire loads). This means, by definition … Read more
Say I write some data, and then I write an indication that the data is now ready. It’s imperative that no other thread who sees the indication that the data is ready not see the write of the data itself. So prior writes cannot move past that write. Say I read that some data is … Read more
One of the issues is the definition of “memory location”, that allows (and forces the compiler to support) locking different structure members by different locks. There is a discussion about a RL problem caused by this. Basically the issue is that having a struct defined like this: struct x { long a; unsigned int b1; … Read more
As I understand this is covered in: 1.10 Multi-threaded executions and data races Para 5: The library defines a number of atomic operations (Clause 29) and operations on mutexes (Clause 30) that are specially identified as synchronization operations. These operations play a special role in making assignments in one thread visible to another. A synchronization … Read more
Lockfree programming is about progress guarantees: From strongest to weakest, those are wait-free, lock-free, obstruction-free, and blocking. A guarantee is expensive and comes at a price. The more guarantees you want, the more you pay. Generally, a blocking algorithm or datastructure (with a mutex, say) has the greatest liberties, and thus is potentially the fastest. … Read more
The spinlock mutex implementation looks okay to me. I think they got the definitions of acquire and release completely wrong. Here is the clearest explanation of acquire/release consistency models that I am aware of: Gharachorloo; Lenoski; Laudon; Gibbons; Gupta; Hennessy: Memory consistency and event ordering in scalable shared-memory multiprocessors, Int’l Symp Comp Arch, ISCA(17):15-26, 1990, … Read more
The C++ memory model is the specification of when and why physical memory is read/written with respect to C++ code. Until the next C++ standard, the C++ memory model is the same as C. In the C++0x standard, a proper memory model for multithreading is expected to be included (see here), and it will be … Read more
TL:DR: On every modern ISA that has byte-store instructions (including x86), they’re atomic and don’t disturb surrounding bytes. (I’m not aware of any older ISAs where byte-store instructions could “invent writes” to neighbouring bytes either.) The actual implementation mechanism (in non-x86 CPUs) is sometimes an internal RMW cycle to modify a whole word in a … Read more
The C++11 memory ordering parameters for atomic operations specify constraints on the ordering. If you do a store with std::memory_order_release, and a load from another thread reads the value with std::memory_order_acquire then subsequent read operations from the second thread will see any values stored to any memory location by the first thread that were prior … Read more