The high order bits are reserved in case the address bus would be increased in the future, so you can’t use it simply like that The AMD64 architecture defines a 64-bit virtual address format, of which the low-order 48 bits are used in current implementations (…) The architecture definition allows this limit to be raised … Read more
Memory access through pointers is said to be more efficient than memory access through an array. That may have been true in the past when compilers were relatively stupid beasts. You only need to look at some of the code output by gcc in high optimisation modes to know that it is no longer true. … Read more
Here is an attempt to provide insight into the relative cost of cache misses by analogy with baking chocolate chip cookies … Your hands are your registers. It takes you 1 second to drop chocolate chips into the dough. The kitchen counter is your L1 cache, twelve times slower than registers. It takes 12 x … Read more
It’s likely that this information applies only to compute capabality 1.x, or cuda 2.0. More recent architectures and cuda 3.0 have more sophisticated global memory access and in fact “coalesced global loads” are not even profiled for these chips. Also, this logic can be applied to shared memory to avoid bank conflicts. A coalesced memory … Read more
watch only breaks on write, rwatch let you break on read, and awatch let you break on read/write. You can set read watchpoints on memory locations: gdb$ rwatch *0xfeedface Hardware read watchpoint 2: *0xfeedface but one limitation applies to the rwatch and awatch commands; you can’t use gdb variables in expressions: gdb$ rwatch $ebx+0xec1a04f Expression … Read more