Wildcard targets in a Makefile

The concept is called pattern rules. You can read about it in GNU make manual. $(GRAPHDIR)/%.png: $(GRAPHDIR)/%.dot dot $< -Tpng -o $@ graphs: $(patsubst %,$(GRAPHDIR)/%.png, Complex Simple IFileReader McCabe)\ or just %.png: %.dot dot $< -Tpng -o $@ graphs: $(patsubst %,$(GRAPHDIR)/%.png, Complex Simple IFileReader McCabe) You can also remove all repetition by extracting one of … Read more

Why use build tools like Autotools when we can just write our own makefiles?

You are talking about two separate but intertwined things here: Autotools GNU coding standards Within Autotools, you have several projects: Autoconf Automake Libtool Let’s look at each one individually. Autoconf Autoconf easily scans an existing tree to find its dependencies and create a configure script that will run under almost any kind of shell. The … Read more

Disable make builtin rules and variables from inside the make file

Disabling the built-in rules is done by writing an empty rule for .SUFFIXES: .SUFFIXES: Having erased the built-in rules, I’m not sure that erasing the built-in variables helps you much more than just remembering to set them yourself or not use them, but you could use something like $(foreach V, $(shell make -p -f/dev/null 2>/dev/null … Read more

Append to GNU make variables via command line

Check out the override directive. You will probably need to modify the makefile once, but it should do what you want. Example makefile: override CFLAGS += -Wall app: main.c gcc $(CFLAGS) -o app main.c Example command lines: $ make gcc -Wall -o app main.c $ make CFLAGS=-g gcc -g -Wall -o app main.c

Debugging GNU make

make -d should give you more than enough information to debug your makefile. Be warned: it will take some time and effort to analyze the output but loading the output into your favorite editor and doing searches will assist a lot. You can greatly reduce the amount of debugging output if you specify the specific … Read more