Back in the “old days” when performance was always a concern, it made more sense. It was used in communication to verify integrity (do error checking) and a substantial portion of communication was serial, which makes more use of parity than parallel communications. In any case, it was trivial for the CPU to compute it … Read more
Could somebody please help me understand how CMOV improves branching? Well, it does NOT improve branching, it removes it. A CMOV could be seen as two instructions in one, a MOV and a NOP. Which one is executed depends on the flags. So internally it may look like if (cond) { mov dst, src } … Read more
(Some of this is x86 and Intel-specific. Most of the key points apply to any CPU that does hardware page walks. I also discuss ISAs like MIPS that handle TLB misses with software.) Modern x86 microarchitectures have dedicated page-walk hardware. They can even speculatively do page-walks to load TLB entries before a TLB miss actually … Read more
First, terminology: Usually, at Intel at least, an interrupt is something that comes from the outside world. Usually it is not synchronized with instructions executing on the processor, i.e. it is an asynchronous external interrupt. In Intel terminology an exception is something caused by instructions executing on the processor. E.g. a page fault, or an … Read more
The main reason is: performance. Another reason is power consumption. Separate dCache and iCache makes it possible to fetch instructions and data in parallel. Instructions and data have different access patterns. Writes to iCache are rare. CPU designers are optimizing the iCache and the CPU architecture based on the assumption that code changes are rare. … Read more
Rotates are required for bit shifts across multiple words. When you SHL the lower word, the high-order bit spills out into the carry. To complete the operation, you need to shift the higher word(s) while bringing in the carry to the low-order bit. RCL is the instruction that accomplishes this. High word Low word CF … Read more
You can’t access it directly because there’s no legitimate use case. Having any arbitrary instruction change eip would make branch prediction very difficult, and would probably open up a whole host of security issues. You can edit eip using jmp, call or ret. You just can’t directly read from or write to eip using normal … Read more
Why is the range of unsigned byte is from -128 to 127? It’s not. An unsigned byte (assuming 8-bit) is from 0 to 255. The range of a signed byte using 2’s complement is from -128 to 127, directly from the definition of 2’s complement: 01111111 = +127 01111110 = +126 01111101 = +125 … … Read more
General claim is modern systems have better branch predictors and compilers are much more advanced so their cost on instruction encoding space is not justified. This is from ARMv8 Instruction Set Overview The A64 instruction set does not include the concept of predicated or conditional execution. Benchmarking shows that modern branch predictors work well enough … Read more
I would assume that it’s indicating packages compiled for little-endian and hard-float ABI as appropriate – i.e. it’s a software thing and only tangentially related to the hardware. In other words, you don’t actually have an “armv7l” processor – you have an ARMv7 processor which may well have a hardware FPU (and can run big-endian … Read more