What are perf cache events meaning?

Some answers:

  • L1 is the Level-1 cache, the smallest and fastest one. LLC on the other hand refers to the last level of the cache hierarchy, thus denoting the largest but slowest cache.
  • i vs. d distinguishes instruction cache from data cache. Only L1 is split in this way, other caches are shared between data and instructions.
  • TLB refers to the translation lookaside buffer, a cache used when mapping virtual addresses to physical ones.
  • Different TLB counters depending on whether the named address referred to an instruction or some data.
  • For all data access, different counters are kept depending on whether the given memory location was read, written, or prefetched (i.e. retrieved for reading at some later time).
  • The number of misses indicates how often a given item of data was accessed but not present in the cache.

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