I write code for FPGAs, not ASICS… but TDD is my still my preferred approach. I like to have a full suite of tests for all the functional code I write, and I try (not always successfully) to write testcode first. Staring at waveforms always happens at some point when you’re debugging, but it’s not … Read more
$finish exits the simulation and gives control back to the operating system. $stop suspends the simulation and puts a simulator in an interactive mode.
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Generally, the idea behind the localparam (added to the Verilog-2001 standard) is to protect value of localparam from accidental or incorrect redefinition by an end-user (unlike a parameter value, this value can’t be modified by parameter redefinition or by a defparam statement). Based on IEEE 1364-2005 (ch. 4.10.2): Verilog HDL local parameters are identical to … Read more
Verilog thinks in bits, so reg [7:0] a[0:3] will give you a 4×8 bit array (=4×1 byte array). You get the first byte out of this with a[0]. The third bit of the 2nd byte is a[1][2]. For a 2D array of bytes, first check your simulator/compiler. Older versions (pre ’01, I believe) won’t support … Read more
Some data types in Verilog, such as reg, are 4-state. This means that each bit can be one of 4 values: 0,1,x,z. With the “case equality” operator, ===, x’s are compared, and the result is 1. With ==, the result of the comparison is not 0, as you stated; rather, the result is x, according … Read more
The curly braces mean concatenation, from most significant bit (MSB) on the left down to the least significant bit (LSB) on the right. You are creating a 32-bit bus (result) whose 16 most significant bits consist of 16 copies of bit 15 (the MSB) of the a bus, and whose 16 least significant bits consist … Read more
Wire:- Wires are used for connecting different elements. They can be treated as physical wires. They can be read or assigned. No values get stored in them. They need to be driven by either continuous assign statement or from a port of a module. Reg:- Contrary to their name, regs don’t necessarily correspond to physical … Read more
reg and wire specify how the object will be assigned and are therefore only meaningful for outputs. If you plan to assign your output in sequential code,such as within an always block, declare it as a reg (which really is a misnomer for “variable” in Verilog). Otherwise, it should be a wire, which is also … Read more
Sort of an old thread, but wanted to put in my $0.02. This isn’t really specific to Verilog/VHDL.. more on hardware design in general… specifically synthesizable design for custom ASICs. This is my opinion based on years of industry (as opposed to academic) experience on design. They are in no particular order My umbrella statement … Read more