Hans and DarkDust answer covered i386/i686 and amd64/x86_64, so there’s no sense in revisiting them. This answer will focus on X32, and provide some info learned after a X32 port. x32 is an ABI for amd64/x86_64 CPUs using 32-bit integers, longs and pointers. The idea is to combine the smaller memory and cache footprint from … Read more
Here is an article over at software.intel.com on that sheds little light on user level locks: User level locks involve utilizing the atomic instructions of processor to atomically update a memory space. The atomic instructions involve utilizing a lock prefix on the instruction and having the destination operand assigned to a memory address. The following … Read more
Largely, for the same reason you start at the least significant digit (the right end) when you add—because carries propagate toward the more significant digits. Putting the least significant byte first allows the processor to get started on the add after having read only the first byte of an offset. After you’ve done enough assembly … Read more
This is what you are looking for: Assemblers And Loaders – By David Salomon. Published February, 1993 – Freely available (download here) Of course, you are going to need the following: Intel® 64 and IA-32 Architectures Software Developer’s Manuals AMD-64 Architecture Programmers manual Linkers and Loaders by John R. Levine (freely available) ELF File Format … Read more
TL:DR: int 0x80 works when used correctly, as long as any pointers fit in 32 bits (stack pointers don’t fit). But beware that strace decodes it wrong unless you have a very recent strace + kernel. int 0x80 zeros r8-r11 for reasons, and preserves everything else. Use it exactly like you would in 32-bit code, … Read more
When people refer to 32-bit and 64-bit assembly, they’re talking about which instruction set you’ll use – they’re also sometimes called Ia32 and x64 in the Intel case, which I presume you’re asking about. There is a lot more going on in the 64-bit case, so starting with 32-bit is probably good; you just need … Read more
Take a look at section 17.2 of the 80386 Programmer’s Reference Manual. A disassembler is really just a glorified finite-state machine. The steps in disassembly are: Check if the current byte is an instruction prefix byte (F3, F2, or F0); if so, then you’ve got a REP/REPE/REPNE/LOCK prefix. Advance to the next byte. Check to … Read more
Version of this answer with a nice TOC and more content. I will correct any error reported. If you want to make large modifications or add a missing aspect, make them on your own answers to get well deserved rep. Minor edits can be merged directly in. Sample code Minimal example: https://github.com/cirosantilli/x86-bare-metal-examples/blob/5c672f73884a487414b3e21bd9e579c67cd77621/paging.S Like everything else … Read more
As a hobbyist operating system writer, I found that because paging (a major part of the modern protection model) only has a concept of privileged (ring 0,1,2) and unprivileged, the benefit to rings 1 and 2 were diminished greatly. The intent by Intel in having rings 1 and 2 is for the OS to put … Read more
Non-Temporal SSE instructions (MOVNTI, MOVNTQ, etc.), don’t follow the normal cache-coherency rules. Therefore non-temporal stores must be followed by an SFENCE instruction in order for their results to be seen by other processors in a timely fashion. When data is produced and not (immediately) consumed again, the fact that memory store operations read a full … Read more