Yes, see this. Once you have lambda, it’s all downhill from there. Here is a plagiarized Fibonacci example This should be enough to build a foundation for more generality (I’ve got to get back to work, or I’d play more.) dec = $(patsubst .%,%,$1) not = $(if $1,,.) lteq = $(if $1,$(if $(findstring $1,$2),.,),.) gteq … Read more
If file1 does not exist then $(wildcard file1) will evaluate to an empty string. ifeq ($(wildcard file1),) CLEAN_SRC = else CLEAN_SRC = *.h file3 endif
I’ve seen this done at several shops. The most common approach is to use double-colon rules, assuming you’re using something like GNU make. In your common makefile you would have something like this: clean:: # standard cleanup, like remove all .o’s: rm -f *.o Note that there are two colons following clean, not just one! … Read more
Actually, @- and -@ both do work, but will print a make: [target] Error 1 (ignored) warning. Instead, you can use @command || true or, since : is shorthand for true in shell, @command ||: This often a better thing to do, because it avoid Make’s confusing warning that an error was ignored in an … Read more
The variable MAKECMDGOALS contains the list of targets that were specified on the command line, no matter how many (it’s empty if there were none).
dep.o: dep.src config1.cfg config2.cfg @echo the second preq is $(word 2,$^), the third is $(word 3,$^)
In order to really understand the autotools utilities you have to remember where they come from: they come from an open source world where there are (a) developers who are working from a source code repository (CVS, Git, etc.) and creating a tar file or similar containing source code and putting that tar file up … Read more
GNU make provides .VARIABLES which holds all global variables’ names. However, this includes built-in variables(like MAKEFLAGS). If you have to exclude built-in variables, some filtering like the following might be needed. The following makefile prints user-defined variables(CUR-DIR, LOG-DIR) using info: # Place this line at the top of your Makefile VARS_OLD := $(.VARIABLES) # Define … Read more
By default, make does print every command before executing it. This printing can be suppressed by one of the following mechanisms: on a case-by-case basis, by adding @ at the beginning of the command globally, by adding the .SILENT built-in target. somewhere along the make process, by invoking sub-make(s) with one of the flags -s, … Read more
To start with: the actual command must be on the next line (or at least that is the case with GNU Make, it might be different with other Make’s – I’m not sure of that) clean: rm -rf *.o (note, you need a TAB before rm -rf *.o as in every rule) Making it silent … Read more