You should never quote anything because of make. Make doesn’t understand or parse single- or double-quote characters in any way. Every quoting character you write in a makefile will be kept as a literal quote and passed along as-is to the commands that make invokes. So, if the shell expects and can interpret a quoted … Read more
Each :: rule is processed independently, so it can be simpler. For example, the single rule: libxxx.a : sub1.o sub2.o ar rv libxxx.a sub1.o ar rv libxxx.a sub2.o can be replaced with two simpler rules: libxxx.a :: sub1.o ar rv libxxx.a sub1.o libxxx.a :: sub2.o ar rv libxxx.a sub2.o Utilities like AutoMake have an easier … Read more
Strictly speaking, it doesn’t necessarily do anything. If a Makefile has a target named check, then make check will “build” that target. It’s typically a phony target, meaning that it is a make-scripted command rather than a file named “check” that gets created. The gnu project advises that all gnu software should include a make … Read more
Each command runs in its own subshell, so variables can’t survive from one command to the next. Put them on the same line and they’ll work: build: @read -p “Enter Module Name:” module; \ module_dir=./modules/$$module; \ mkdir -p $$module_dir/build
Line 18 is gcc -fPIC -g -c -Wall mymemory.cpp. Make is expecting a separator, typically :. It’s not detecting this line as a command. You mistyped the intendation: you have spaces where you should have a tab. Good editors highlight makefile lines that begin with spaces but look like they should begin with a tab … Read more
By default, the order of execution is the same as specified in the prerequisites list, unless there are any dependencies defined between these prerequisites. abc: x y z The order is x y z. abc: x y z y : z The order would be x z y. But ideally, you should design your Makefiles … Read more
When you run make, you’re instructing it to essentially follow a set of build steps for a particular target. When make is called with no parameters, it runs the first target, which usually simply compiles the project. make install maps to the install target, which usually does nothing more than copy binaries into their destinations. … Read more
You should be able to use the MAKEFILE_LIST variable, like this: # This must be the first line in Makefile.common TOP := $(dir $(firstword $(MAKEFILE_LIST))) From the documentation: As make reads various makefiles, including any obtained from the MAKEFILES variable, the command line, the default files, or from include directives, their names will be automatically … Read more
Look at Make’s addsuffix function. Here is an example we use with `addsuffix` to place obj files one directory below the source. SOURCE += MainThread.cpp SOURCE += Blah.cpp OBJ=$(join $(addsuffix ../obj/, $(dir $(SOURCE))), $(notdir $(SOURCE:.cpp=.o))) From the make manual: $(addprefix prefix,names…) The argument names is regarded as a series of names, separated by whitespace; prefix … Read more
Um, no, $PWD is sometimes defined in your environment and thus inherited by make, but oftentimes not. You need $CURDIR. DIR := ${CURDIR}