The MSDN documentation includes information about the x64 registers. x64 extends x64’s 8 general-purpose registers to be 64-bit, and adds 8 new 64-bit registers. The 64-bit registers have names beginning with “r”, so for example the 64-bit extension of eax is called rax. The new registers are named r8 through r15. The lower 32 bits, … Read more
gcc actually produces assembler and assembles it using the as assembler. Not all compilers do this – the MS compilers produce object code directly, though you can make them generate assembler output. Translating assembler to object code is a pretty simple process, at least compared with C→Assembly or C→Machine-code translation. Some compilers produce other high-level … Read more
Yes, they do require the machine code and all memory operands. Shouldn’t the CPU access the memory pages sequentially, i.e. first read the instruction and then access the memory operand? Yes that’s logically what happens, but a page-fault exception interrupts that 2-step process and discards any progress. The CPU doesn’t have any way to remember … Read more
I spoke to an AMD engineer at the Microsoft Build conference about this error, and showed him my repro. He emailed me this morning: We have investigated and found that this is due to a known errata in the Llano APU family. It can be fixed via a BIOS update depending on the OEM – … Read more
You can use Cargo’s cargo rustc command to send arguments to rustc directly: cargo rustc — –emit asm ls target/debug/deps/<crate_name>-<hash>.s For optimized assembly: cargo rustc –release — –emit asm ls target/release/deps/<crate_name>-<hash>.s If you see multiple <crate_name>-<hash>-<hash>.rcgu.s files instead of a <crate_name>-<hash>.s file, disable incremental compilation by setting the environment variable CARGO_INCREMENTAL=0.
Just for some clarification. In the early microprocessor days of the 1970’s, CPUs had only a small number of registers and a very limited instruction set. Typically, the arithmetic unit could only operate on a single CPU register, often referred to as the “accumulator”. The accumulator on the 8 bit 8080 & Z80 processors was … Read more
As the DWARF spec says in section 6.4: […] The call frame is identified by an address on the stack. We refer to this address as the Canonical Frame Address or CFA. Typically, the CFA is defined to be the value of the stack pointer at the call site in the previous frame (which may … Read more
[L1] means the memory contents at address L1. After running mov al, [L1] here, The al register will receive the byte at address L1 (the letter ‘w’).
Caller-saved registers (AKA volatile registers, or call-clobbered) are used to hold temporary quantities that need not be preserved across calls. For that reason, it is the caller’s responsibility to push these registers onto the stack or copy them somewhere else if it wants to restore this value after a procedure call. It’s normal to let … Read more
In general for any kind of vector horizontal reduction, extract / shuffle high half to line up with low, then vertical add (or min/max/or/and/xor/multiply/whatever); repeat until a there’s just a single element (with high garbage in the rest of the vector). If you start with vectors wider than 128-bit, narrow in half until you get … Read more