I use Emacs+VHDL-mode which is great if you don’t mind (or have already climbed) the learning curve of Emacs. Alternatively, you could try Sigasi-HDT which is Eclipse-based and has more GUI. And some more powerful refactoring tools by the look of it.
I suggest, you have good background in Digital Design. If not, start with any edition of “Digital Design” book or, alternatively “Contemporary logic design”. Download GHDL (VHDL compiler/simulator using GCC technology) or a little more friendly software tool boot. Learn how to build a VHDL program with GHDL. Try to compile simple “Hello, world!”. Learn … Read more
I write code for FPGAs, not ASICS… but TDD is my still my preferred approach. I like to have a full suite of tests for all the functional code I write, and I try (not always successfully) to write testcode first. Staring at waveforms always happens at some point when you’re debugging, but it’s not … Read more
QuestaSim’s vsim executable on Windows cannot cope with Windows paths (using \ as path delimiter sign) in the -modelsimini command line switch. The path needs to be in posix writing (using / delimiters). As far as I can see, vcom has no problems with the correct path delimiter sign.
Variables are used when you want to create serialized code, unlike the normal parallel code. (Serialized means that the commands are executed in their order, one after the other instead of together). A variable can exist only inside a process, and the assignment of values is not parallel. For example, consider the following code: signal … Read more
The problem is that you are using multiple non-blocking statements to assign the signal. sig_2_o0 <= ‘0’; sig_2_o0 <= ‘1’; This translates to: at next event assign ‘0’ to sig_2_o0. at next event assign ‘1’ to sig_2_o0. This is different than using blocking assignments: sig_2_o0 := ‘0’; sig_2_o0 := ‘1’; Which would translate to: assign … Read more
My favoured technique: signal clk : std_logic := ‘0’; — make sure you initialise! … clk <= not clk after half_period; I usually extend this with a finished signal to allow me to stop the clock: clk <= not clk after half_period when finished /= ‘1’ else ‘0’; If you use a std_logic item for … Read more
rising_edge is defined as: FUNCTION rising_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN IS BEGIN RETURN (s’EVENT AND (To_X01(s) = ‘1’) AND (To_X01(s’LAST_VALUE) = ‘0’)); END; FUNCTION To_X01 ( s : std_ulogic ) RETURN X01 IS BEGIN RETURN (cvt_to_x01(s)); END; CONSTANT cvt_to_x01 : logic_x01_table := ( ‘X’, — ‘U’ ‘X’, — ‘X’ ‘0’, — ‘0’ ‘1’, … Read more
Sort of an old thread, but wanted to put in my $0.02. This isn’t really specific to Verilog/VHDL.. more on hardware design in general… specifically synthesizable design for custom ASICs. This is my opinion based on years of industry (as opposed to academic) experience on design. They are in no particular order My umbrella statement … Read more