Some data types in Verilog, such as reg, are 4-state. This means that each bit can be one of 4 values: 0,1,x,z. With the “case equality” operator, ===, x’s are compared, and the result is 1. With ==, the result of the comparison is not 0, as you stated; rather, the result is x, according … Read more
Wire:- Wires are used for connecting different elements. They can be treated as physical wires. They can be read or assigned. No values get stored in them. They need to be driven by either continuous assign statement or from a port of a module. Reg:- Contrary to their name, regs don’t necessarily correspond to physical … Read more
Sort of an old thread, but wanted to put in my $0.02. This isn’t really specific to Verilog/VHDL.. more on hardware design in general… specifically synthesizable design for custom ASICs. This is my opinion based on years of industry (as opposed to academic) experience on design. They are in no particular order My umbrella statement … Read more