What Name to Give Your Makefile chapter of GNU Make manual clarifies it: By default, when make looks for the makefile, it tries the following names, in order: GNUmakefile, makefile and Makefile. Normally you should call your makefile either makefile or Makefile. (We recommend Makefile because it appears prominently near the beginning of a directory … Read more
You should never quote anything because of make. Make doesn’t understand or parse single- or double-quote characters in any way. Every quoting character you write in a makefile will be kept as a literal quote and passed along as-is to the commands that make invokes. So, if the shell expects and can interpret a quoted … Read more
Note: This answer focuses on the aspect of a robust recursive invocation of a different target in a given makefile. To complement Jack Kelly’s helpful answer, here’s a GNU makefile snippet that demonstrates the use of $(MAKE) to robustly invoke a different target in the same makefile (ensuring that the same make binary is called, … Read more
Each :: rule is processed independently, so it can be simpler. For example, the single rule: libxxx.a : sub1.o sub2.o ar rv libxxx.a sub1.o ar rv libxxx.a sub2.o can be replaced with two simpler rules: libxxx.a :: sub1.o ar rv libxxx.a sub1.o libxxx.a :: sub2.o ar rv libxxx.a sub2.o Utilities like AutoMake have an easier … Read more
Each command runs in its own subshell, so variables can’t survive from one command to the next. Put them on the same line and they’ll work: build: @read -p “Enter Module Name:” module; \ module_dir=./modules/$$module; \ mkdir -p $$module_dir/build
Line 18 is gcc -fPIC -g -c -Wall mymemory.cpp. Make is expecting a separator, typically :. It’s not detecting this line as a command. You mistyped the intendation: you have spaces where you should have a tab. Good editors highlight makefile lines that begin with spaces but look like they should begin with a tab … Read more
By default, the order of execution is the same as specified in the prerequisites list, unless there are any dependencies defined between these prerequisites. abc: x y z The order is x y z. abc: x y z y : z The order would be x z y. But ideally, you should design your Makefiles … Read more
When you run make, you’re instructing it to essentially follow a set of build steps for a particular target. When make is called with no parameters, it runs the first target, which usually simply compiles the project. make install maps to the install target, which usually does nothing more than copy binaries into their destinations. … Read more
There are 3 related concepts: call function multi-line variables conditionals The refactored result could look like this: ifeq ($(UNAME),Linux) compile = $(MAKE) FC=$(1) FFLAGS=$(2) PETSC_FFLAGS=$(3) \ TARGET=$@ LEXT=”$(1)_$(UNAME)” -e syst else define compile = echo $(err_arch) exit 1 endef endif debug_ifort: $(call compile,ifort,$(difort),”…”) That one \ that is left is to continue the $(MAKE) line … Read more
Um, no, $PWD is sometimes defined in your environment and thus inherited by make, but oftentimes not. You need $CURDIR. DIR := ${CURDIR}