I suggest, you have good background in Digital Design. If not, start with any edition of “Digital Design” book or, alternatively “Contemporary logic design”. Download GHDL (VHDL compiler/simulator using GCC technology) or a little more friendly software tool boot. Learn how to build a VHDL program with GHDL. Try to compile simple “Hello, world!”. Learn … Read more
QuestaSim’s vsim executable on Windows cannot cope with Windows paths (using \ as path delimiter sign) in the -modelsimini command line switch. The path needs to be in posix writing (using / delimiters). As far as I can see, vcom has no problems with the correct path delimiter sign.
Variables are used when you want to create serialized code, unlike the normal parallel code. (Serialized means that the commands are executed in their order, one after the other instead of together). A variable can exist only inside a process, and the assignment of values is not parallel. For example, consider the following code: signal … Read more
rising_edge is defined as: FUNCTION rising_edge (SIGNAL s : std_ulogic) RETURN BOOLEAN IS BEGIN RETURN (s’EVENT AND (To_X01(s) = ‘1’) AND (To_X01(s’LAST_VALUE) = ‘0’)); END; FUNCTION To_X01 ( s : std_ulogic ) RETURN X01 IS BEGIN RETURN (cvt_to_x01(s)); END; CONSTANT cvt_to_x01 : logic_x01_table := ( ‘X’, — ‘U’ ‘X’, — ‘X’ ‘0’, — ‘0’ ‘1’, … Read more