Here’s how to do it: You can execute a shell command in a Makefile using (); E.g. echoTarget: (echo “I’m an echo”) Just be sure to put a tab character before each line in the shell command. i.e. you will need a tab before (echo “I’m an echo”) Here’s what will work for activating virtualenv: … Read more
make -s should do what you’re after a bit more neatly. I don’t know of a way to force it on the makefiles, but the GNU manual might have one. Failing that you could check the Linux kernel build system, since that seems to automatically hide stdout.
You need to use the $(shell operation) command in make. If you use operation, then the shell command will get evaluated every time. If you are writing to a log file, you don’t want the log file name to change every time you access it in a single make command. LOGPATH = logs LOGFILE = … Read more
Okay, I needed something similar. The path to my output artifacts were quite long, but I wanted short target names and also benefit easily from bash-completion. Here is what I’m came up with: os := [arbitrary long path to an artifact] platform := [arbitrary long path to a differ artifact] packer := [common parts of … Read more
Names of these variables originate from names of the corresponding tools. Usually the meaning of these abbreviations is the following: CC stands for “C compiler” (in GCC abbreviation it is also treated as “compiler collection”). LD is a linker (comes from “link editor” or from “loader”). These are also commonly used in makefiles (see Implicit … Read more
First, let’s recall what the ordinary prerequisites are. Basically, the prerequisites in Makefile have two functions: They are checked and, if necessary, are built before the target If any of the prerequisites gets rebuilt (or is simply newer than the target) then the target will also be rebuilt. Now, the order-only prerequisites do item 1, … Read more
If your make is GNU-make and all the defined variables include a non-space character, ifdef VAR1 && VAR2 && VAR3 can be written as ifneq ($(and $(VAR1),$(VAR2),$(VAR3)),) On a related note, probably and function requires version 3.81 or later. In case some defined variables may be empty strings, if we prepare the following functions: ifndef_any_of … Read more
Yes, a Makefile can have a directory as target. Your problem could be that the cd doesn’t do what you want: it does cd and the git clone is carried out in the original directory (the one you cded from, not the one you cded to). This is because for every command in the Makefile … Read more
SRCS = $(wildcard *.c) PROGS = $(patsubst %.c,%,$(SRCS)) all: $(PROGS) %: %.c $(CC) $(CFLAGS) -o $@ $<
Newer versions of GCC have an -MP option which can be used with -MD. I simply added -MP and -MD to the CPPFLAGS variable for my project (I did not write a custom recipe for compiling C++) and added an “-include $(SRC:.cpp=.d)” line. Using -MD and -MP gives a dependency file which includes both the … Read more