Why does make think the target is up to date?

Maybe you have a file/directory named test in the directory. If this directory exists, and has no dependencies that are more recent, then this target is not rebuild. To force rebuild on these kind of not-file-related targets, you should make them phony as follows: .PHONY: all test clean Note that you can declare all of … Read more

Make error: missing separator

As indicated in the online manual, the most common cause for that error is that lines are indented with spaces when make expects tab characters. Correct target: \tcmd where \t is TAB (U+0009) Wrong target: ….cmd where each . represents a SPACE (U+0020).

What are Makefile.am and Makefile.in?

Makefile.am is a programmer-defined file and is used by automake to generate the Makefile.in file (the .am stands for automake). The configure script typically seen in source tarballs will use the Makefile.in to generate a Makefile. The configure script itself is generated from a programmer-defined file named either configure.ac or configure.in (deprecated). I prefer .ac … Read more

How do I write the ‘cd’ command in a makefile?

It is actually executing the command, changing the directory to some_directory, however, this is performed in a sub-process shell, and affects neither make nor the shell you’re working from. If you’re looking to perform more tasks within some_directory, you need to add a semi-colon and append the other commands as well. Note that you cannot … Read more

What’s the opposite of ‘make install’, i.e. how do you uninstall a library in Linux?

make clean removes any intermediate or output files from your source / build tree. However, it only affects the source / build tree; it does not touch the rest of the filesystem and so will not remove previously installed software. If you’re lucky, running make uninstall will work. It’s up to the library’s authors to … Read more

What do the makefile symbols $@ and $< mean?

$@ is the name of the target being generated, and $< the first prerequisite (usually a source file). You can find a list of all these special variables in the GNU Make manual. For example, consider the following declaration: all: library.cpp main.cpp In this case: $@ evaluates to all $< evaluates to library.cpp $^ evaluates … Read more

Passing additional variables from command line to make

You have several options to set up variables from outside your makefile: From environment – each environment variable is transformed into a makefile variable with the same name and value. You may also want to set -e option (aka –environments-override) on, and your environment variables will override assignments made into makefile (unless these assignments themselves … Read more

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