gnu-make

Note: This answer focuses on the aspect of a robust recursive invocation of a different target in a given makefile. To complement Jack Kelly’s helpful answer, here’s a GNU makefile snippet that demonstrates the use of $(MAKE) to robustly invoke a different target in the same makefile (ensuring that the same make binary is called, … Read more

I think make -j will respect the dependencies you specify in your Makefile; i.e. if you specify that objA depends on objB and objC, then make won’t start working on objA until objB and objC are complete. Most likely your Makefile isn’t specifying the necessary order of operations strictly enough, and it’s just luck that … Read more