Section 2.2 of the NASM documentation is titled Quick Start for MASM Users which lists the important differences between NASM and MASM. NASM version 2.15 added some MASM compatibility, including a %use masm macro package. See section 6.5 masm: MASM compatibility. Even without the macro package, ? and DUP work in data directives like db, … Read more
NASM actually uses its own variation of Intel syntax, different from the MASM syntax used in Intel’s official documentation. The opcode names and operand orders are the same as in Intel so the instructions look the same at first glance, but any significant program will have differences. For example with MASM the instruction used by … Read more
I think this is a valid question. It can be a bit hard to find up to date information on assembler. Yes. A lot of resources printed and online describe i386 (x86) assembler and not the new amd64 (x86_64). Many things have changed, e.g. function arguments used to be passed on the stack but now … Read more
For ecx repetitions, stores the contents of eax into where edi points to, incrementing or decrementing edi (depending on the direction flag) by 4 bytes each time. Normally, this is used for a memset-type operation. Usually, that instruction is simply written rep stosd. Experienced assembly coders know all the details mentioned above just by seeing … Read more
wow, this turned out to be a lot more painful than I expected. 100% of the pain was linux protecting the program from being overwritten and/or executing data. Two solutions shown below. And a lot of googling was involved so the somewhat simple put some instruction bytes and execute them was mine, the mprotect and … Read more
In the decoders and uop-cache, addressing mode doesn’t affect micro-fusion (except that an instruction with an immediate operand can’t micro-fuse a RIP-relative addressing mode). But some combinations of uop and addressing mode can’t stay micro-fused in the ROB (in the out-of-order core), so Intel SnB-family CPUs “un-laminate” when necessary, at some point before the issue/rename … Read more
There is a performance difference, especially for enter. On modern processors this decodes to some 10 to 20 µops, while the three instruction sequence is about 4 to 6, depending on the architecture. For details consult Agner Fog’s instruction tables. Additionally the enter instruction usually has a quite high latency, for example 8 clocks on … Read more
Each routine uses a portion of the stack, and we call it a stack frame. Although an assembler programmer is not forced to follow the following style, it is highly recommended as good practice. The stack frame for each routine is divided into three parts: function parameters, back-pointer to the previous stack frame, and local … Read more
These registers were originally implicitly used in repetitive instructions, for instance MOVSB, which copy a byte from DS:SI (DataSegment:SourceIndex) to ES:DI(ExtraSegment:DestinationIndex), at the time of the 16-bits computers with segmented memory in real mode. And also as index registers in 16-bit addressing modes like [bx + si]. Right now, these registers are for example used … Read more
ORG is used to set the assembler location counter. This may or may not translate to a load address at link time. It can be used to define absolute addresses, e.g. when defining something like interrupt vectors which may need to be at a fixed address, or it can be used to introduce padding or … Read more