How to use a variable list as a target in a Makefile?

Question

Yes. There are what are known as pattern rules. An example is the easiest to understand:

%.o: %.cpp
       $(CC) -c $(CFLAGS) $(CPPFLAGS) $< -o $@

(remember that Makefiles require tabs). This rule describes how to make an object file from a cpp file.

If you do not want such a broad rule, you can use what are called static patterns:

objects = file1.o file2.o file3.o

all: $(objects)

$(objects): %.o: %.cpp
        $(CC) -c $(CFLAGS) $(CPPFLAGS) $< -o $@

Here’s the section on static pattern rules and pattern rules in the GNU Make manual.