VHDL – How should I create a clock in a testbench?
My favoured technique: signal clk : std_logic := ‘0’; — make sure you initialise! … clk <= not clk after half_period; I usually extend this with a finished signal to allow me to stop the clock: clk <= not clk after half_period when finished /= ‘1’ else ‘0’; If you use a std_logic item for … Read more